Cache random access memory (RAM) is an expensive resource on a silicon chip and sharing a cache generally provides the best utilisation of the RAM. If a cache is shared among multiple concurrently running applications or threads then partitioning limits destructive interference, provides quality of service guarantees, and maximises utility.
Flexible partitioning or re-partitioning is required to support multiple use cases or system modes. For example, in a mobile platform, heterogeneous semiconductor intellectual property cores may share a cache but have differing quality of service requirements and would interfere with one another if the cache were not partitioned. Examples of systems benefiting from cache partitioning are: real time and best effort threads in networking applications; virtual machines in server applications; real-time and safety-critical threads in automotive applications; and those comprising central processor units (CPU); and graphical processor units (GPU).
Cache partitioning benefits the maximising of utility of the cache. Traditionally, cache partitioning is done by constraining placement, for example, way partitioning.
Partitioning based on controlling cache line replacement is preferable to partitioning by constraining placement because it permits fine-grained control of partition size, need not reduce associativity, and allows for easier re-sizing.
Some cache replacement policies attempt to partition the cache between thrashing and reused lines by inserting lines at different priorities. They are not able to partition the cache for purposes of quality of service and non-interference.
The present techniques seek to provide improvements over the prior art.